AD7533_04 Ver la hoja de datos (PDF) - Intersil
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AD7533_04 Datasheet PDF : 8 Pages
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AD7533
2. Monitor VOUT for a -VREF (1 - 1/210) reading.
3. To increase VOUT, connect a series resistor, R2, (0Ω to
250Ω) in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, R1, (0Ω to
250Ω) between the reference voltage and the VREF
terminal.
Bipolar (Offset Binary) Operation
The circuit configuration for operating the AD7533 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values, 4-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 2.
A “Logic 1” input at any digital input forces the
corresponding ladder switch to steer the bit current to
IOUT1 bus. A “Logic 0” input forces the bit current to IOUT2
bus. For any code the IOUT1 and IOUT2 bus currents are
complements of one another. The current amplifier at
IOUT2 changes the polarity of IOUT2 current and the
transconductance amplifier at IOUT1 output sums the two
currents. This configuration doubles the output range. The
difference current resulting at zero offset binary code,
(MSB = “Logic 1”, all other bits = “Logic 0”), is corrected by
using an external resistor, (10MΩ), from VREF to IOUT2 .
±10V +15V
VREF
R1
R2
MSB
15
4
14 RFEEDBACK
16
DATA
INPUTS
AD7533 1 IOUT1
-
IOUT2 R4 5K
R3 5K
13 3 2
LSB
CR1
6
+
R6 10MΩ
-
CR2
6
+
VOUT
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
TABLE 2. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB
(NOTE 2)
NOMINAL ANALOG OUTPUT
1111111111
-VREF
55----11---12--
1000000001
-VREF
5----11---2--
1000000000
0
0111111111
+VREF
5----11---2--
0000000001
+VREF
55----11---12--
0000000000
+VREF
55----11---22--
NOTES:
12. VOUT as shown in Figure 3.
13. Nominal Full Scale for the circuit of Figure 3 is given by:
FSR
=
VR
E
F
1--5--0--1-2--2--3-
.
14. Nominal LSB magnitude for the circuit of Figure 3 is given by:
LSB
=
VREF
5----11---2--
.
Offset Adjustment
5. Adjust VREF to approximately +10V.
6. Connect all digital inputs to “Logic 1”.
7. Adjust IOUT2 amplifier offset adjust trimpot for 0V ±1mV at
IOUT2 amplifier output.
8. Connect MSB (Bit 1) to “Logic 1” and all other bits to
“Logic 0”.
9. Adjust IOUT1 amplifier offset adjust trimpot for 0V ±1mV at
VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1 - 2-9) volts reading.
3. To increase VOUT, connect a series resistor (R2) of up to
250Ω between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resistor (R1) of up to
250Ω between the reference voltage and the VREF
terminal.
5
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