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LTC2140I

12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs

Linear Technology 

LTC2142-12/

LTC2141-12/LTC2140-12

APPLICATIONS INFORMATION

1.25V

LTC2142-12

VREF

2.2μF

5Ω

1.25V BANDGAP

REFERENCE

0.625V

REFL pins are connected by short jumpers in an internal

layer. To minimize the inductance of these jumpers they

can be placed in a small hole in the GND plane on the

second board layer.

TIE TO VDD FOR 2V RANGE;

TIE TO GND FOR 1V RANGE;

3"/(&


t
7SENSE FOR

0.625V < VSENSE < 1.300V

SENSE

C2

– + REFH

0.1μF

+ – REFL

C1

– + REFH

RANGE

DETECT

AND

CONTROL

BUFFER

INTERNAL ADC

HIGH REFERENCE

0.8x

DIFF AMP

C3

0.1μF

+ – REFL

C1: 2.2μF LOW INDUCTANCE

INTERDIGITATED CAPACITOR

TDK CLLE1AX7S0G225M

MURATA LLA219C70G225M

AVX W2L14Z225M

OR EQUIVALENT

INTERNAL ADC

LOW REFERENCE

21421012 F08a

Figure 8a. Reference Circuit

Alternatively C1 can be replaced by a standard 2.2μF

capacitor between REFH and REFL (see Figure 8b). The

capacitors should be as close to the pins as possible (not

on the back side of the circuit board).

Figure 8c and Figure 8d show the recommended circuit

board layout for the REFH/REFL bypass capacitors. Note

that in Figure 8c, every pin of the interdigitated capacitor

(C1) is connected since the pins are not internally connected

in some vendors’ capacitors. In Figure 8d the REFH and

C3

0.1μF

C1

2.2μF

LTC2142-12

REFH

REFL

REFH

C2

0.1μF

REFL

CAPACITORS ARE 0402 PACKAGE SIZE

21421012 F08b

Figure 8b. Alternative REFH/REFL Bypass Circuit

Figure 8c. Recommended Layout for the REFH/REFL

Bypass Circuit in Figure 8a

Figure 8d. Recommended Layout for the REFH/REFL

Bypass Circuit in Figure 8b

1.25V

EXTERNAL

REFERENCE

VREF

2.2μF

SENSE

LTC2142-12

1μF

21421012 F09

Figure 9. Using an External 1.25V Reference

Encode Inputs

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals – do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

The differential encode mode is recommended for si-

nusoidal, PECL, or LVDS encode inputs (Figure 12 and

Figure 13). The encode inputs are internally biased to 1.2V

through 10k equivalent resistance. The encode inputs can

be taken above VDD (up to 3.6V), and the common mode

range is from 1.1V to 1.6V. In the differential encode mode,

21421012p

21

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