QL8025-6PV100I Ver la hoja de datos (PDF) - QuickLogic Corporation

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QL8025-6PV100I

Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM

QuickLogic Corporation 

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A programmable Weak Pull-Down resistor is available on each I/O. The I/O Weak Pull-Down

eliminates the need for external pull down resistors for used I/Os. The spec for pull-down current

is maximum of 150 µA under worst case condition.

I/O Output Logic

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There are a maximum of eight global clock networks in each Eclipse-II device. Global clocks can

drive logic cells and I/O registers, ECUs, and RAM blocks in the device. All global clocks have

access to a Quad Net (local clock network) connection with a programmable connection to the

logic cell’s register clock input.

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