BA6664FM Ver la hoja de datos (PDF) - ROHM Semiconductor

Número de pieza

componentes Descripción

fabricante

BA6664FM

1ch Spindle Motor Driver ICs

ROHM Semiconductor 

BA6859AFP-Y,BA6664FM,BD6671FM

Technical Note

(8) ASO

When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.

(9) Thermal shutdown circuit (TSD)

This IC incorporates a TSD circuit. If the chip becomes the following temperature, coil output to the motor will be open.

The TSD circuit is designed only to shut the IC off to prevent runaway thermal operation. It is not designed to protect the

IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment

where the operation of the TSD circuit is assumed.

BA6859AFP-Y

BA6664FM

BD6671FM

TSD ON temperature [℃] (typ.)

175

175

170

Hysteresis temperature [℃] (typ.)

25

15

25

(10) Regarding input pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.

P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of

parasitic elements.

For example, when the resistors and transistors are connected to the pins as shown in Fig. 18,

○the P/N junction functions as a parasitic diode

when GND > (Pin A) for the resistor or GND > (Pin B) for the transistor (NPN).

○Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described above combines

with the N layer of other adjacent elements to operate as a parasitic NPN transistor.

The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result

of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC

malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will

trigger the operation of parasitic elements, such as by the application of voltages lower than the GND (P substrate)

voltage to input pins.

Pin A

Resistor

Pin A

Transistor (NPN)

Pin B

C

B

Pin B

E

N P+ N

Parasitic element

P

P+ N

P substrate

GND

Parasitic

element

N P+

NP

P+ N

P substrate

Parasitic element GND

GND

Fig.18 Example of IC structure

B

C

E

GND

Other adjacent

elements

Parasitic

element

(11) Testing on application boards

When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.

Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,

and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to

or removing it from a jig or fixture during the inspection process.

(12) Ground Wiring Pattern

When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,

placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage

variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change

the GND wiring pattern of any external parts, either.

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2010.06 - Rev.A

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