QL7100-5PQ208C Ver la hoja de datos (PDF) - QuickLogic Corporation
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QL7100-5PQ208C Datasheet PDF : 65 Pages
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EclipsePlus Family Data Sheet Rev. A
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—
these functions require high logic cell usage while garnering only moderate performance results.
The EclipsePlus Family architecture allows for functionality above and beyond that achievable using
programmable logic devices. By embedding a dynamically reconfigurable computational unit, the device can
address various arithmetic functions efficiently. This approach offers greater performance than traditional
programmable logic implementations. The embedded block is implemented at the transistor level as shown in
Figure 2.
RESET
S1
S2
S3
CIN
SIGN1
SIGN2
A[0:7]
A[8:15]
Figure 2: ECU Block Diagram
D
C
3-4
decoder
B
A
8-bit
2-1
Multiplier
mux
16-bit
Adder
DQ
17 inc. 17-bit
COUT Register
00
01
3-1
mux
10
Q[0:16]
A[0:15]
CLK
B[0:15]
2-1
mux
The EclipsePlus ECU blocks (Table 2) are placed next to the SRAM circuitry for efficient memory/instruction
fetch and addressing for DSP algorithmic implementations.
Table 2: Eclipse II ECU Blocks
Device
QL7180
QL7160
QL7120
QL7100
ECUs
18
16
12
10
Up to 18 8-bit Multiply-Accumulate (MAC) functions can be implemented per cycle for a total of up to
1.8 billion MACs/s when clocked at 100 MHz. Additional MAC functions can be implemented in the
programmable logic.
© 2006 QuickLogic Corporation
www.quicklogic.com
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