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MC33035 Datasheet PDF : 24 Pages
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MC33035
Figure 20. Three Phase, Six Step Commutation Truth Table (Note 1)
Inputs (Note 2)
Outputs (Note 3)
Sensor Electrical Phasing (Note 4)
Top Drives
Bottom Drives
60°
120°
SA SB SC SA SB SC
1
00
1
10
1
11
0
11
0
01
0
00
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
Current
F/R Enable Brake Sense AT BT
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
0
0
1
CT AB BB CB Fault
1
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
1
0
1
1
0
1
0
1
(Note 5)
F/R = 1
1
00
1
0
0
0
1
0
1
10
1
1
0
0
1
0
1
11
0
1
0
0
1
0
0
11
0
1
1
0
1
0
0
01
0
0
1
0
1
0
0
00
1
0
1
0
1
0
0
1
1
0
1
0
0
1
(Note 5)
0
1
1
0
0
1
0
1
F/R = 0
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
01
1
1
1
X
X
0
0
10
0
0
0
X
X
0
X
1
1
1
0
0
0
0
(Note 6)
X
1
1
1
0
0
0
0
Brake = 0
1
01
1
1
1
X
X
1
0
10
0
0
0
X
X
1
X
1
1
1
1
1
1
0
(Note 7)
X
1
1
1
1
1
1
0
Brake = 1
V
VV
V
V
V
X
1
1
X
1
1
1
1
1
1
1
(Note 8)
V
VV
V
V
V
X
0
1
X
1
1
1
1
1
1
0
(Note 9)
V
VV
V
V
V
X
0
0
X
1
1
1
0
0
0
0
(Note 10)
V
VV
V
V
V
X
1
0
1
1
1
1
0
0
0
0
(Note 11)
NOTES: 1. V = Any one of six valid sensor or drive combinations X = Don’t care.
2. The digital inputs (Pins 3, 4, 5, 6, 7, 22, 23) are all TTL compatible. The current sense input (Pin 9) has a 100 mV threshold with respect to Pin 15.
A logic 0 for this input is defined as < 85 mV, and a logic 1 is > 115 mV.
3. The fault and top drive outputs are open collector design and active in the low (0) state.
4. With 60°/120° select (Pin 22) in the high (1) state, configuration is for 60° sensor electrical phasing inputs. With Pin 22 in low (0) state, configuration
is for 120° sensor electrical phasing inputs.
5. Valid 60° or 120° sensor combinations for corresponding valid top and bottom drive outputs.
6. Invalid sensor inputs with brake = 0; All top and bottom drives off, Fault low.
7. Invalid sensor inputs with brake = 1; All top drives off, all bottom drives on, Fault low.
8. Valid 60° or 120° sensor inputs with brake = 1; All top drives off, all bottom drives on, Fault high.
9. Valid sensor inputs with brake = 1 and enable = 0; All top drives off, all bottom drives on, Fault low.
10. Valid sensor inputs with brake = 0 and enable = 0; All top and bottom drives off, Fault low.
11. All bottom drives off, Fault low.
Pulse Width Modulator
The use of pulse width modulation provides an energy
efficient method of controlling the motor speed by varying the
average voltage applied to each stator winding during the
commutation sequence. As CT discharges, the oscillator sets
both latches, allowing conduction of the top and bottom drive
outputs. The PWM comparator resets the upper latch,
terminating the bottom drive output conduction when the
positive–going ramp of CT becomes greater than the error
amplifier output. The pulse width modulator timing diagram is
shown in Figure 21. Pulse width modulation for speed control
appears only at the bottom drive outputs.
Current Limit
Continuous operation of a motor that is severely
over–loaded results in overheating and eventual failure.
This destructive condition can best be prevented with the
use of cycle–by–cycle current limiting. That is, each
on–cycle is treated as a separate event. Cycle–by–cycle
current limiting is accomplished by monitoring the stator
current build–up each time an output switch conducts, and
upon sensing an over current condition, immediately turning
off the switch and holding it off for the remaining duration of
oscillator ramp–up period. The stator current is converted to
a voltage by inserting a ground–referenced sense resistor RS
(Figure 36) in series with the three bottom switch transistors
(Q4, Q5, Q6). The voltage developed across the sense
resistor is monitored by the Current Sense Input (Pins 9 and
15), and compared to the internal 100 mV reference. The
current sense comparator inputs have an input common
mode range of approximately 3.0 V. If the 100 mV current
sense threshold is exceeded, the comparator resets the
lower sense latch and terminates output switch conduction.
The value for the current sense resistor is:
+ RS
0.1
Istator(max)
The Fault output activates during an over current condition.
The dual–latch PWM configuration ensures that only one
single output conduction pulse occurs during any given
oscillator cycle, whether terminated by the output of the error
amp or the current limit comparator.
Figure 21. Pulse Width Modulator Timing Diagram
Capacitor CT
Error Amp Out/
PWM Input
Current
Sense Input
Latch “Set”
Inputs
Top Drive
Outputs
Bottom Drive
Outputs
Fault Output
10
MOTOROLA ANALOG IC DEVICE DATA
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