MT46V16M16TG-75Z Ver la hoja de datos (PDF) - Micron Technology
Número de pieza
componentes Descripción
fabricante
MT46V16M16TG-75Z Datasheet PDF : 80 Pages
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256Mb: x4, x8, x16
DDR SDRAM
Figure 50: Bank Write - Without Auto Precharge
CK#
CK
CKE
COMMAND5
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
A10
T0
tIS tIH
tIS tIH
NOP6
BA0, BA1
T1
tCK
T2
T3 T3n T4 T4n T5 T5n T6
tCH tCL
ACT
tIS tIH
RA
RA
NOP6
RA
tIS tIH
Bank x
tRCD
tRAS
WRITE2
Col n
NOP6
tIS tIH
3
Bank x
NOP6
NOP6
T7
T8
NOP6
PRE
tWR
ALL BANKS
ONE BANK
Bank x4
tRP
tDQSS (NOM)
DQS
tWPRES tWPRE
8
tDQSL tDQSH tWPST
DQ1
DI
b
DM
tDS
tDH
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DI n = data-in from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = Row Address; and BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. See Figure 43, Data Input Timing, on page 68, for detailed DQ timing.
8. Although not required by the Micron device, JEDEC specifies that DQS be a valid HIGH, LOW or some point on a valid
transition on or before this clock edge (T3n).
SYMBOL
tCH
tCL
tCK (2.5)
tCK (2)
tIHF
tISF
-6/6T/6T
MIN MAX
0.45 0.55
0.45 0.55
6
13
7.5 13
0.75
0.75
-75E/75Z
MIN MAX
0.45 0.55
0.45 0.55
7.5 13
7.5 13
0.90
0.90
-75
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
10
13
0.90
0.90
UNITS
tCK
tCK
ns
ns
ns
ns
SYMBOL
tIHS
tISS
tMRD
tRFC
tRP
tVTD
-6/6T/6T
MIN MAX
0.8
0.8
15
72
18
0
-75E/75Z
MIN MAX
1
1
15
75
15
0
-75
MIN MAX
1
1
15
75
20
0
UNITS
ns
ns
ns
ns
ns
ns
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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