MT46V16M16TG-75Z Ver la hoja de datos (PDF) - Micron Technology
Número de pieza
componentes Descripción
fabricante
MT46V16M16TG-75Z Datasheet PDF : 80 Pages
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CK#
CK
CKE
COMMAND4
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
A10
BA0, BA1
DM
256Mb: x4, x8, x16
DDR SDRAM
Figure 49: Bank Read - With Auto Precharge
T0
T1
T2
T3
T4
T5 T5n T6 T6n T7
T8
tIS tIH
tCK
tCH tCL
tIS tIH
NOP5
ACT
NOP5
READ2,6
NOP5
NOP5
NOP5
NOP5
ACT
tIS tIH
RA
Col n
RA
RA
RA
IS IH
Bank x
tRCD, tRAP6
tRAS
tRC
3
tIS tIH
Bank x
CL = 2
tRP7
RA
RA
Bank x
Case 1: tAC (MIN) and tDQSCK (MIN)
DQS
DQ1
Case 2: tAC (MAX) and tDQSCK (MAX)
DQS
DQ1
tLZ(MIN)
tRPRE
tDQSCK (MIN)
tLZ (MIN)
DO
n
tAC (MIN)
tDQSCK (MAX)
tRPRE
tRPST
tRPST
DO
n
tAC (MAX)
tHZ (MAX)
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE; RA = Row Address; and BA = Bank Address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these times.
6. The READ command can only be applied at T3 if tRAP is satisfied at T3.
7. tRP starts only after tRAS has been satisfied.
8. Refer to Figure 40 on page 65, Figure 41 on page 66, and Figure 42 on page 67 for detailed DQS and DQ timing.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
74
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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