256Mb: x4, x8, x16
DDR SDRAM
Figure 43: Data Input Timing
CK#
CK
DQS
DQ
DM
T03
T1 T1n T2 T2n T3
tDQSS
tDSH1 tDSS2 tDSH1 tDSS2
tWPRES tWPRE
DI
b
tDQSL tDQSH tWPST
tDS
tDH
TRANSITIONING DATA
DON’T CARE
NOTE:
1. tDSH (MIN) generally occurs during tDQSS (MIN).
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
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