ADAU1451 Ver la hoja de datos (PDF) - Analog Devices
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ADAU1451 Datasheet PDF : 180 Pages
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Data Sheet
ADAU1452/ADAU1451/ADAU1450
Auxiliary ADC
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, AVDD = 3.3 V ± 10%, IOVDD = 1.8 V − 10% to 3.3 V + 10%, unless otherwise noted.
Table 5.
Parameter
RESOLUTION
FULL-SCALE ANALOG INPUT
NONLINEARITY
Integrated Nonlinearity (INL)
Differential Nonlinearity (DNL)
GAIN ERROR
INPUT IMPEDANCE
SAMPLE RATE
Min
Typ
Max
Unit
10
Bits
AVDD
V
−2
+2
LSB
−2
+2
LSB
−2
+2
LSB
200
kΩ
fCORE/6144
Hz
TIMING SPECIFICATIONS
Master Clock Input
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%, unless otherwise noted.
Table 6.
Parameter
MASTER CLOCK INPUT (MCLK)
fMCLK
tMCLK
tMCLKD
tMCLKH
tMCLKL
CLKOUT Jitter
CORE CLOCK
fCORE
ADAU1452 and ADAU1451
ADAU1450
tCORE
ADAU1452 and ADAU1451
ADAU1450
Min
2.375
27.8
25
0.25 × tMCLK
0.25 × tMCLK
12
Max
36
421
75
0.75 × tMCLK
0.75 × tMCLK
106
Unit Description
MHz MCLK frequency
ns
MCLK period
%
MCLK duty cycle
ns
MCLK width high
ns
MCLK width low
ps
Cycle-to-cycle rms average
152
294.912
MHz System (DSP core) clock frequency; PLL
feedback divider ranges from 64 to 108
76
147.456
MHz System (DSP core) clock frequency; PLL
feedback divider ranges from 64 to 108
3.39
ns
System (DSP core) clock period
6.78
ns
System (DSP core) clock period
tMCLK
MCLK
Reset
tMCLKH
tMCLKL
Figure 3. Master Clock Input Timing Specifications
TA = −40°C to +105°C, DVDD = 1.2 V ± 5%, IOVDD = 1.8 V − 10% to 3.3 V + 10%.
Table 7.
Parameter
RESET
tWRST
Min
Max
Unit
Description
10
ns
Reset pulse width low
RESET
tWRST
Figure 4. Reset Timing Specification
Rev. C | Page 9 of 180
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