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ZPSD311V-B-25

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD3XX Family

8.0

Operating

Modes (MCU

Configurations)

(cont.)

Table 3. Bus and Port Configuration Options

8-bit Data Bus

Port A

Port B

AD0/A0–AD7/A7

AD8/A8–AD15/A15

Multiplexed Address/Data

I/O or low-order address

lines or Low-order multiplexed

address/data byte

I/O and/or CS0–CS7

Low-order multiplexed

address/data byte

High-order address

bus byte

Non-Multiplexed Address/Data

D0–D7 data bus byte

I/O and/or CS0–CS7

Low-order address bus byte

High-order address bus byte

16-bit Data Bus

Port A

Port B

AD0/A0–AD7/A7

AD8/A8–AD15/A15

I/O or low-order address

lines or low-order multiplexed

address/data byte

I/O and/or CS0–CS7

Low-order multiplexed

address/data byte

High-order multiplexed

address/data byte

Low-order data bus byte

High-order data bus byte

Low-order address bus byte

High-order address bus byte

9.0

Programmable

Address

Decoder (PAD)

The PSD3XX contains two programmable arrays, referred to as PAD A and PAD B

(Figure 4). PAD A is used to generate chip select signals derived from the input address to

the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals.

PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the

decoding to select external devices or as a random logic replacement.

PAD A and PAD B receive the same inputs. The PAD logic is configured by PSDsoft

based on the designer’s input. The PAD’s non-volatile configuration is stored in a

re-programmable CMOS EPROM. Windowed packages are available for erasure by the

user. See Table 4 for a list of PAD A and PAD B functions.

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