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AD8114-EVAL

Low Cost 225 MHz 16 × 16 Crosspoint Switches

Analog Devices 

AD8114/AD8115

TIMING CHARACTERISTICS (SERIAL)

Table 2. Timing Characteristics

Parameter

Serial Data Setup Time

CLK Pulse Width

Serial Data Hold Time

CLK Pulse Separation, Serial Mode

CLK to UPDATE Delay

UPDATE Pulse Width

CLK to DATA OUT Valid, Serial Mode

Propagation Delay, UPDATE to Switch On or Off

Data Load Time, CLK = 5 MHz, Serial Mode

CLK, UPDATE Rise and Fall Times

RESET Time

Symbol

t1

t2

t3

t4

t5

t6

t7

–

–

–

–

Min

Typ

Max

Unit

20

ns

100

ns

20

ns

100

ns

0

ns

50

ns

200

ns

50

ns

16

µs

100

ns

200

ns

Table 3. Logic Levels

VIH

VIL

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

2.0 V min

0.8 V max

VOH

DATA OUT

2.7 V min

VOL

DATA OUT

0.5 V max

IIH

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

20 µA max

IIL

RESET, SER/PAR

CLK, DATA IN,

CE, UPDATE

−400 µA min

IOH

DATA OUT

−400 µA max

IOL

DATA OUT

3.0 mA min

1

CLK

0

1

DATA IN

0

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

t2

t1

t3

OUT7 (D4)

t7

t4

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

OUT7 (D3)

OUT00 (D0)

t5

t6

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

Figure 2. Timing Diagram, Serial Mode

Rev. B | Page 5 of 32

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