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74ALVT16823DL,518

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Nexperia B.V. All rights reserved 

Nexperia

Table 8. Measurement points

VCC

Input

VM

≤ 2.7 V

0.5 x VCC

≥ 3.0 V

1.5 V

74ALVT16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Output

VM

0.5 x VCC

1.5 V

VX

VOL + 0.15 V

VOL + 0.3 V

VY

VOH - 0.15 V

VOH - 0.3 V

VI 90 %

tW

negative

pulse

VM

10 %

0V

tf

VI

positive

pulse

tr

90 %

VM

10 %

0V

tW

VI

G

VCC

VO

DUT

RT

VM

tr

tf

VM

VEXT

RL

CL

RL

001aae331

Test data is given in Table 9.

Definitions test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Figure 9. Test circuit for measuring switching times

Table 9. Test data

Input

VI

fi

3.0 V or VCC

≤ 10 MHz

whichever is less

tW

500 ns

tr, tf

≤ 2.5 ns

Load

CL

50 pF

RL

500 Ω

VEXT

tPHZ, tPZH

GND

tPLZ, tPZL

tPLH, tPHL

6 V or VCC x 2 open

74ALVT16823

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 22 January 2018

© Nexperia B.V. 2018. All rights reserved.

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