74LV374D,118 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74LV374D,118 Datasheet PDF : 17 Pages
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NXP Semiconductors
74LV374
Octal D-type flip-flop; positive edge-trigger; 3-state
6. Functional description
Table 3. Function table[1]
Operating mode
Input
OE
CP
Dn
Load and read register
L
↑
l
L
↑
h
Load register and disable H
↑
l
outputs
H
↑
h
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition
Z = high-impedance OFF-state
↑ = LOW to HIGH clock transition
7. Limiting values
Internal flip-flop Output
Qn
L
L
H
H
L
Z
H
Z
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
Tamb = −40 °C to +125 °C
DIP20
−0.5
[1] -
[1] -
-
-
−70
−65
[2]
-
+7.0 V
±20
mA
±50
mA
±35
mA
70
mA
-
mA
+150 °C
750 mW
SO20, SSOP20 and TSSOP20
-
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP20 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO20 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
74LV374_2
Product data sheet
Rev. 02 — 14 May 2009
© NXP B.V. 2009. All rights reserved.
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