CY7C1383D-133BZXC(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor

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fabricante

CY7C1383D-133BZXC
(Rev.:2004)

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

Cypress Semiconductor 

PRELIMINARY

CY7C1381D

CY7C1383D

Timing Diagrams

Read Cycle Timing[25]

tCYC

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

X

CE

ADV

t CH t CL

tADS tADH

tADS tADH

tAS tAH

A1

A2

t WES tWEH

tCES tCEH

t

ADVS

tADVH

ADV suspends burst

OE

Data Out (Q)

tOEV

High-Z

tCLZ

tCDV

tOEHZ

Q(A1)

tOELZ

tCDV

tDOH

Q(A2) Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Single READ

Note:

22. This parameter is sampled and not 100% tested.

DON’T CARE

BURST

READ

UNDEFINED

Deselect Cycle

Q(A2) Q(A2 + 1)

Burst wraps around

to its initial state

tCHZ

Q(A2 + 2)

Document #: 38-05544 Rev. *A

Page 22 of 29

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