Table 54. PWM Output Timing Parameter: MATT Mode 24 MHz Crystal Clock
Ref No.
Parameter
1
System CLK frequency1
2a
Clock high time
2b
Clock low time
3a
Clock fall time
3b
Clock rise time
4a
Output delay time
4b
1 CL of PWMO = 30 pF
Output setup time
Minimum
24
20.99
21.01
—
—
—
15.92
Maximum
24
—
—
0.3
0.3
15.23
—
Unit
MHz
ns
ns
ns
ns
ns
ns
3.5.12 Serial Audio Interface (SAIF) AC Timing
The following subsections describe SAIF timing in two cases:
• Transmitter
• Receiver
3.5.12.1 SAIF Transmitter Timing
Figure 33 shows the timing for SAIF transmitter with internal clock, and Table 55 describes the timing
parameters (SS1–SS13).
SS1
SS5
SS3
SS2
SS4
BITCLK
LRCLK
SDATA0-2
SS6
SS10
SS8 SS11
SS13
SS7
SS9
SS12
Figure 33. SAIF Transmitter Timing Diagram
i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1
Freescale Semiconductor
51