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MAX8778

Dual Quick-PWM Step-Down Controller with Low-Power LDO, RTC Regulator

Maxim Integrated 

Dual Quick-PWM Step-Down Controller

with Low-Power LDO, RTC Regulator

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, no load on LDO, RTC, OUT1, OUT2, and REF, VIN = 12V, VDD = VCC = VSECFB = 5V, VREFIN2 = 1.0V, BYP =

LDOREFIN = GND, ONLDO = IN, ON1 = ON2 = VCC, TA = -40°C to +85°C, unless otherwise noted.) (Note 3)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

OUT2 Undervoltage-Protection

Trip Threshold

PGOOD2 Lower Trip Threshold

Preset mode: with respect to error-comparator

VUVP(OUT2) threshold

Tracking mode: with respect to REFIN2 voltage

Preset mode: with respect to error-comparator

threshold, falling edge, hysteresis = 1%

Tracking mode: with respect to REFIN2

voltage, falling edge, hysteresis = 12mV

63

-230

-20

-185

77

%

-370

mV

-12

%

-115

mV

PGOOD2 Output-Low Voltage

VOUT2 = VREFIN2 - 150mV (PGOOD2 low

impedance), ISINK = 4mA

CURRENT LIMIT

ILIM_ Adjustment Range

VILIM

0.2

RILIM_ = 100kΩ

40

Valley Current-Limit Threshold

(Adjustable)

VVALLEY VAGND - VLX_

RILIM_ = 200kΩ

85

RILIM_ = 400kΩ

164

GATE DRIVERS

DH_ Gate Driver On-Resistance

RDH BST1 - LX1 and BST2 - LX2 forced to 5V

DL_ Gate Driver On-Resistance

DL1, DL2; high state

RDL

DL1, DL2; low state

INPUTS AND OUTPUTS

0.4

V

2.0

V

60

115

mV

236

3.5

Ω

4.5

Ω

1.5

TON Input Logic Levels

SKIP Input Logic Levels

ON_ Input Logic Levels

ONLDO Input Logic Levels

High

REF or open

Low

High (forced-PWM)

Open (ultrasonic)

Low (skip)

High (SMPS on)

Low (SMPS off)

High (LDO on)

Low (LDO off)

VCC -

0.4V

1.6

VCC -

0.4V

1.6

2.4

2.4

3.0

V

0.4

3.0

V

0.4

V

0.8

V

0.8

Note 1: DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduc-

tion, the MAX17020 regulates the valley of the output ripple, so the actual DC output voltage is higher than the trip level by

50% of the output ripple voltage. In discontinuous conduction (IOUT < ILOAD(SKIP)), the output voltage has a DC regulation

level higher than the error-comparator threshold by approximately 1.5% due to slope compensation.

Note 2: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST = 5V,

and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times might be differ-

ent due to MOSFET switching speeds.

Note 3: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design

and characterization.

Note 4: Specifications increased by 1Ω to account for test measurement error.

_______________________________________________________________________________________ 9

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