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SMJ4C1024SV Datasheet PDF : 27 Pages
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SMJ4C1024
1048576 BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS023E – DECEMBER 1988 – REVISED MARCH 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level
output voltage
IOH = – 5 mA
VOL
Low-level
output voltage IOL = 4.2 mA
II
Input current VCC = 5.5 V, VI = 0 V to 6.5 V,
(leakage)
All other pins = 0 V to VCC
IO
Output
current
(leakage)
VCC = 5.5 V, VO = 0 V to VCC,
CAS high
ICC1
Read- or
write-cycle
current
VCC = 5.5 V, Minimum cycle
ICC2
ICC3
Standby
current
Average
refresh
current
(RAS only or
CBR)
After one memory cycle,
RAS and CAS high,
VIH = 2.4 V
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
ICC4
Average page VCC = 5.5 V, tPC = minimum,
current
RAS low,
CAS cycling
’4C1024-80 ’4C1024-10
MIN MAX MIN MAX
2.4
2.4
0.4
0.4
± 10
± 10
± 10
± 10
75
70
3
3
70
65
50
45
’4C1024-12
MIN MAX
2.4
0.4
± 10
± 10
60
3
55
35
’4C1024-15
UNIT
MIN MAX
2.4
V
0.4 V
± 10 µA
± 10 µA
55 mA
3 mA
50 mA
30 mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
HL / JD / FQ
MIN MAX
HJ
MIN MAX
HK
MIN MAX
SV
UNIT
MIN MAX
Ci(A) Input capacitance, address inputs
6
7
8
9 pF
Ci(D) Input capacitance, data input
5
5
6
7 pF
Ci(RC) Input capacitance, strobe inputs
7
7
8
8 pF
Ci(W) Input capacitance, write-enable input
7
7
7
7 pF
Co
Output capacitance
7
9
10
8 pF
NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25°C with a 1-MHz signal
applied to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
ALT.
’4C1024-80 ’4C1024-10 ’4C1024-12
SYMBOL MIN MAX MIN MAX MIN MAX
ta(C)
ta(CA)
ta(R)
ta(CP)
tdis(CH)
Access time from CAS low
Access time from column address
Access time from RAS low
Access time from column precharge
Output disable time after CAS high
(see Note 4)
tCAC
tAA
tRAC
tCPA
tOFF
20
25
30
40
45
55
80
100
120
40
40
60
20
25
30
NOTE 4: tdis(CH) is specified when the output is no longer driven. The output is disabled by bringing CAS high.
’4C1024-15
MIN MAX
40
70
150
75
35
UNIT
ns
ns
ns
ns
ns
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
7
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