ADUC7033 Ver la hoja de datos (PDF) - Analog Devices

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ADUC7033

Integrated, Precision Battery Sensor for Automotive

Analog Devices 

Detailed bit definitions for most of these MMRs have been

listed previously. In addition to the registers described in the

LIN MMR Description section, LHSCAP and LHSCMP are

registers that are required for the operation of the BSD

interface. Details of these registers follow.

LIN Hardware Synchronization Capture Register

Name:

LHSCAP

Address:

0xFFFF0794

Default Value: 0x0000

Access:

Read only

Function:

The 16-bit, read only LHSCAP register holds

the last captured value of the internal LIN

synchronization timer (LHSVAL0). In BSD

mode, the LHSVAL0 is clocked directly from

an internal 5 MHz clock; its value is loaded

into the capture register on every falling edge

of the BSD bus.

LIN Hardware Synchronization Compare Register

Name:

LHSCMP

Address:

0xFFFF0798

Default Value: 0x0000

Access:

Read/write

Function:

The LHSCMP register is used to time BSD

output pulse widths. When enabled through

LHSCON0[5], a LIN interrupt is generated

when the value in LHSCAP equals the value

written in LHSCMP. This functionality allows

user code to determine how long a BSD

transmission bit (SYNC, 0, or 1) should be

asserted on the bus.

BSD COMMUNICATIONS FRAME

To transfer data between a master and slave, or vice versa, the

construction of a BSD frame is required. A BSD frame contains

seven key components: pause/sync, direction bit, the slave

address, the register address, data, Parity Bit 1 (P1) and Parity

Bit 2 (P2), and the acknowledge from the slave.

If the master is transmitting data, then all bits except the

acknowledge bit, are transmitted by the master.

If the master is requesting data from the slave, the master

transmits the pause/sync, the direction bit, slave address,

register address, and P1 bits.

ADuC7033

The slave then transmits the data bytes, P2, and the

acknowledge in the following sequence:

1. PAUSE: ≥3 synchronization pulses.

2. DIR: signifies the direction of data transfer.

a. Zero (0) if master sends request.

b. One (1) if slave sends request.

3. Slave Address.

4. Register Address: defines register to be read or written.

5. Bit 3 is set to write, cleared to read.

6. Data: 8-bit read-only receive register.

7. P1 and P2.

a. P1 = 0 if even number of 1s in 8 previous bits.

b. P1 = 1 if odd number of 1s in 8 previous bits.

c. P2 = 0 if even number of 1s in data-word.

d. P2 = 1 if odd number of 1s in data-word.

8. Acknowledge: zero (0) if transmission is successful.

The acknowledge is always transmitted by the slave to indicate

if the information was received or transmitted.

Table 97. BSD Protocol Description

Slave

Register

Pause DIR Address Address P1 Data P2 ACK

3 bits 1 bit 3 bits

4 bits

1 bit 8 bits 1 bit 1 bit

BSD Example Pulse Widths

An example of the different pulse widths is shown in Figure 5.

For each bit, the period for which the bus is held low defines

what type of bit it is. If the bit is a sync bit, the pulse is held low

for one bit. If the bit is a zero bit, the pulse is held low for three

bits. If the bit is a one bit, the pulse is held low for six bits.

If the master is transmitting data, the signal is held low for the

duration of the signal by the master. An example of a master

transmitting zero is shown in Figure 5. If the slave is transmit-

ting data, the master pulls the bus low to begin communications.

The slave must then pull the bus low before tSYNC elapses and

hold the bus low until either t0 or t1 has elapsed, after which time

the bus is released by the slave. An example of a slave trans-

mitting a zero is shown in Figure 5.

tSYNC

t0

t1

Figure 53. BSD Bit Transmission

BUS PULLED LOW

BY MASTER

BUS RELEASED BY

MASTER AFTER t0

tSYNC

t0

Figure 54. BSD Master Transmitting Zero

Rev. B | Page 131 of 140

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