1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
PROTOCOL
SCL
SDA
START
CONDITION
(S)
tSU;STA
tBUF
BIT 7
MSB
(A7)
tLOW
tHIGH
BIT 6
(A6)
1/fSCL
tr
tf
tHD;STA
Figure 3. I2C Bus Timing Diagram
tSU;DAT
tHD;DAT
+
VSWin
-
DEVICE
VSW
ISWout
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
tVD;DAT
tVD;ACK
tSU;STO
Figure 4. Switch Output Voltage and Current
(VDD = +5V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
VSW vs. SUPPLY VOLTAGE
5.5
5.0 ISWout = 100µA
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.3
3.1
3.9
4.7
5.5
VDD (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
100
fSCL = 400kHz
80
ENHANCED MODE
60
40
BASIC MODE
20
0
2.3
3.1
3.9
4.7
5.5
VDD (V)
SUPPLY CURRENT vs. SCL FREQUENCY
100
80
60
ENHANCED MODE
40
BASIC MODE
20
0
0
100
200
300
400
fSCL (kHz)
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