MAX7358 Ver la hoja de datos (PDF) - Maxim Integrated
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MAX7358
Maxim Integrated
MAX7358 Datasheet PDF : 22 Pages
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1-to-8 I2C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3) (continued)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
PARAMETER
Data Valid Time
Data Valid Acknowledge
Low-Level Reset Time
Reset Time
Recovery to Start
SYMBOL
tVD;DAT
tVD:ACK
tWL(rst)
trst
tREC;STA
CONDITIONS
(High to low)
(Low to high)
MIN TYP MAX
1
0.6
1
5
500
0
UNITS
µs
µs
ns
ns
ns
TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3)
(VDD = 2.3V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
PARAMETER
Propagation Delay from SDA to
SD_ or SCL to SC_
SCL Clock Frequency
Bus Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition After this Period,
the First Clock Pulse is Generated
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Setup Time for a STOP Condition
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals
Fall Time of Both SDA and SCL
Signals
Capacitive Load for Each Bus
Line
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
Data Valid Time
Data Valid Acknowledge
Low-Level Reset Time
Reset Time
Recovery to START
SYMBOL
tPD
fSCL
tBUF
(Note 7)
CONDITIONS
tHD;STA
tLOW
tHIGH
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
(Note 8)
tR
tF
Cb
tSP
tVD;DAT
tVD;ACK
tWL(rst)
trst
tREC;STA
(High to low)
(Low to high)
MIN TYP MAX UNITS
0.3
ns
0
400
kHz
1.3
µs
0.6
1.3
0.6
0.6
0.6
0
100
20 +
0.1Cb
20 +
0.1Cb
µs
µs
µs
µs
µs
0.9
µs
ns
300
ns
300
ns
400
pF
50
ns
1
µs
0.6
1
µs
5
ns
500
ns
0
ns
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