MSC8126TMP6400(2007) Ver la hoja de datos (PDF) - Freescale Semiconductor

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MSC8126TMP6400
(Rev.:2007)

Quad Digital Signal Processor

Freescale Semiconductor 

Hardware Design Considerations

• Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three

capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount

at least one of the capacitors directly below the MSC8126 device.

1.2 V

Power supply

or

Voltage Regulator

(Imin = 3 A)

+

-

Maximum IR drop

of 15 mV at 1 A

Lmax = 2 cm

Bulk/Tantalum capacitors

with low ESR and ESL

Note: Use at least three capacitors.

Each capacitor must be at least 150 μF.

One 0.01 µF capacitor

for every 3 core supply

pads.

MSC8122

High frequency capacitors

(very low ESR and ESL)

Figure 33. Core Power Supply Decoupling

Each VCC and VDD pin on the MSC8126 device should have a low-impedance path to the board power supply. Similarly, each

GND pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the

chip. The VCC power supply should have at least four 0.1 µF by-pass capacitors to ground located as closely as possible to the

four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should

be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and

GND planes.

All output pins on the MSC8126 have fast rise and fall times. PCB trace interconnection length should be minimized to

minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to

the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in

synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.

Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to

proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:

VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in

Figure 34. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-µF capacitor should be closest

to VCCSYN, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be

kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN

by a 0.01-µF capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of

the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11,

M12, M13, N11, N12, and N13.

VDD

VCCSYN

10Ω 10nH

10 µF

0.01 µF

Figure 34. VCCSYN Bypass

MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13

Freescale Semiconductor

41

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