
TCK
(Input)
TDI
TMS
(Input)
TDO
(Output)
TDO
(Output)
TCK
(Input)
TRST
(Input)
VIL
710
711
VIH
708
709
Input Data Valid
Output Data Valid
Figure 31. Test Access Port Timing Diagram
713
712
Figure 32. TRST Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
39