MSC8126TMP6400(2007) Ver la hoja de datos (PDF) - Freescale Semiconductor
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MSC8126TMP6400 Datasheet PDF : 48 Pages
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2.5.6.2 DSI Synchronous Mode
Table 19. DSI Inputs—Synchronous Mode
No.
120
121
122
123
124
125
126
127
Notes:
Characteristic
HCLKIN Cycle Time1, 2
HCLKIN high Pulse Width
HCLKIN low Pulse Width
HA[11–29] inputs set-up time
HD[0–63] inputs set-up time
HCID[0–4] inputs set-up time
All other inputs set-up time
All inputs hold time
1. Values are based on a frequency range of 18–100 MHz.
2. Refer to Table 7 for HCLKIN frequency limits.
Expression
HTC
(0.5 ± 0.1) × HTC
(0.5 ± 0.1) × HTC
—
—
—
—
—
Table 20. DSI Outputs—Synchronous Mode
No.
Characteristic
128 HCLKIN high to HD[0–63] output active
129 HCLKIN high to HD[0–63] output valid
130 HD[0–63] output hold time
131 HCLKIN high to HD[0–63] output high impedance
132 HCLKIN high to HTA output active
133 HCLKIN high to HTA output valid
134 HTA output hold time
135 HCLKIN high to HTA high impedance
Electrical Characteristics
Min Max Units
10.0
55.6
ns
4.0
33.3
ns
4.0
33.3
ns
1.2
—
ns
0.4
—
ns
1.3
—
ns
1.2
—
ns
1.5
—
ns
Min Max Units
2.0
—
ns
—
6.3
ns
1.7
—
ns
—
7.6
ns
2.0
—
ns
—
5.9
ns
1.7
—
ns
—
6.3
ns
120
HCLKIN
122
121
123
127
HA[11–29] input signals
124
127
HD[0–63] input signals
125
127
HCID[0–4] input signals
126
127
All other input signals
131
129
128
130
HD[0–63] output signals
133
132
HTA output signal
135
134
Figure 17. DSI Synchronous Mode Signals Timing Diagram
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
31
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