MSC8122TVT4800V(2006) Ver la hoja de datos (PDF) - Freescale Semiconductor

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MSC8122TVT4800V
(Rev.:2006)

Quad Core 16-Bit Digital Signal Processor

Freescale Semiconductor 

4.3 Connectivity Guidelines

Connectivity Guidelines

Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via

resistors to VDDH or GND, except for the following:

• If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals

can be disconnected.

• When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled

either up or down, depending on design requirements.

• HDST can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the

DCR[DSRFA] bit is set.

• When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/

HDBE[1–3] and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].

• When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared,

HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3] must be pulled up.

• When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.

• The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.

• In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):

— BG, DBG, and TS can be left unconnected.

— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus

functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.

— BR must be pulled up.

— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.

• If there is an external bus master (BCR[EBM] = 1):

— BR, BG, DBG, and TS must be pulled up.

— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus

functionality.

• In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In

other modes, they must be pulled up.

Note: The MSC8122 does not support DLL-enabled mode. For the following two clock schemes, ensure that the

DLL is disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set).

• If no system synchronization is required (for example, the design does not use SDRAM), you can use any of

the available clock modes.

• In the CLKIN synchronization mode, use the following connections:

— Connect the oscillator output through a buffer to CLKIN.

— Connect the CLKIN buffer output to the slave device (for example, SDRAM) making sure that the delay

path between the clock buffer to the MSC8122 and the SDRAM is equal (that is, has a skew less than 100

ps).

— Valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31.

MSC8122 Technical Data, Rev. 13

Freescale Semiconductor

4-3

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