HI-8282 Ver la hoja de datos (PDF) - Holt Integrated Circuits
Número de pieza
componentes Descripción
fabricante
HI-8282 Datasheet PDF : 14 Pages
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Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1mhz +0.1% with 60/40 duty cycle
PARAMETER
SYMBOL
LIMITS
MIN
TYP
CONTROL WORD TIMING
Pulse Width - CWSTR
tCWSTR
130
Setup - DATA BUS Valid to CWSTR HIGH
tCWSET
140
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWHLD
0
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
tD/R
Low Speed
tD/R
Delay - D/R LOW to EN L0W
tD/REN
0
Delay - EN LOW to D/R HIGH
tEND/R
Setup - SEL to EN L0W
tSELEN
20
Hold - SEL to EN HIGH
tENSEL
50
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
Pulse Width - EN1 or EN2
tEN
240
Spacing - EN HIGH to next EN L0W
tENEN
50
FIFO TIMING
Pulse Width - PL1 or PL2
tPL
200
Setup - DATA BUS Valid to PL HIGH
tDWSET
110
Hold - PL HIGH to DATA BUS Hi-Z
tDWHLD
20
Spacing - PL1 or PL2
tPL12
0
Delay - PL2 HIGH to TX/R LOW
tTX/R
TRANSMISSION TIMING
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
0
Delay - ENTX HIGH to 429DO or 429D0: High Speed
Delay - ENTX HIGH to 429DO or 429D0: Low Speed
tENDAT
tENDAT
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
0
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
tENPL
0
Hold - PL HIGH to EN HIGH
tPLEN
0
Delay - TX/R LOW to ENTX HIGH
tTX/REN
0
Master Reset Pulse Width
tMR
400
ARINC Data Rate and Bit Timing
UNITS
MAX
ns
ns
ns
16
µs
128
µs
ns
200
ns
ns
ns
200
ns
30
ns
ns
ns
ns
ns
ns
ns
840
ns
µs
25
µs
200
µs
400
ns
ns
ns
ns
ns
ns
± 1%
HOLT INTEGRATED CIRCUITS
4-37
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