ML65245**/ML65L245*
66 MHz
Pentium™ Processor
LATCH
CACHE
(SRAM)
MAIN MEMORY
(DRAM)
LBX DATA
LOCAL BUS
BWE
BMAddr
ML65245 BUFFER
CNTL
WE
MAddr
PCMC
LBX CNTL
PCI™ BUS (33 MHz)
CONTROL
ADDRESS/DATA
CONTROL
ADDRESS
DATA
Figure 6. ML65245 in a main memory application for a Pentium based system. The high drive and low propagation
delay are essential to buffer the write enable and memory addresses to the main memory SIIMMs.
R4X00™
150/75 MHz
CDRAM
or
DRAM
ML65245
CDRAM
or
DRAM
CONTROL
ADDR
ML65245
ML65245
CONTROL
ADDRESS/DATA
MEMORY I/O
CONTROLLER
Figure 7. The ML65245 in a non-cache, main memory RISC application. The main memory could be DRAM or
Cache DRAM. The ML65245 can be used as a data I/O transceiver as well as an address buffer, as shown above.
7