AD8321 Ver la hoja de datos (PDF) - Analog Devices
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AD8321 Datasheet PDF : 20 Pages
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AD8321
LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA, VCC = +9 V; Full Temperature Range)
Parameter
Min
Typ
Max
Unit
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
Logic “1” Current (VINH = 5 V) PD
Logic “0” Current (VINL = 0 V) PD
2.1
0
0
–600
50
–250
5.0
V
0.8
V
20
nA
–100
nA
190
mA
–30
mA
TIMING REQUIREMENTS (Full Temperature Range, VCC = +9 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (TWH)
16.0
Clock Period (TC)
32.0
Setup Time SDATA vs. Clock (TDS)
5.0
Setup Time DATEN vs. Clock (TES)
15.0
Hold Time SDATA vs. Clock (TDH)
5.0
Hold Time DATEN vs. Clock (TEH)
3.0
Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)
ns
ns
ns
ns
ns
ns
10
ns
Specifications subject to change without notice.
SDATA
CLK
TDS
VALID DATA WORD G1
MSB. . . .LSB
TC
TWH
VALID DATA WORD G2
DATEN
TES
TEH
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
TOFF
PD
TGS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
TON
PEDESTAL
Figure 2. Serial Interface Timing
REV. A
SDATA MSB
CLK
VALID DATA BIT
MSB-1
TDS
TDH
MSB-2
Figure 3. SDATA Timing
–3–
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