P4C1256 Ver la hoja de datos (PDF) - Semiconductor Corporation
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P4C1256 Datasheet PDF : 17 Pages
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P4C1256
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
TRUTH TABLE
Mode
Standby
Standby
D Disabled
OUT
Read
Write
CE OE WE
H XX
X XX
L HH
L LH
L XL
I/O
High Z
High Z
High Z
DOUT
High Z
Power
Standby
Standby
Active
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1256, care must be taken when
testing this device; an inadequate setup can cause a normal functioning part
to be rejected as faulty. Long high-inductance leads that cause supply
bounce must be avoided by bringing the VCC and ground planes directly up
to the contactor fingers. A 0.01 µF high frequency capacitor is also required
between VCC and ground. To avoid signal reflections, proper termination
Figure 2. Thevenin Equivalent
must be used; for example, a 50Ω test environment should be terminated
into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input,
and a 116Ω resistor must be used in series with DOUT to match 166Ω
(Thevenin Resistance).
Document # SRAM119 REV G
Page 8 of 17
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