HM-65262/883 Ver la hoja de datos (PDF) - Intersil

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fabricante

HM-65262/883

16K x 1 Asynchronous CMOS Static RAM

Intersil 

Timing Waveforms

HM-65262/883

A

(4) TELQV

E

(21) TEHQZ

(20) TELQX

(22) TEHQX

Q

NOTE:

1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high.

FIGURE 1. READ CYCLE 1: CONTROLLED BY E

(1) TAVAX

A

(2) TAVQV

E

(20) TELQX

Q

(21) TEHQZ

(23) TAXQX

NOTE:

1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid.

FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS

209

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