T4312816A Ver la hoja de datos (PDF) - Taiwan Memory Technology

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fabricante

T4312816A

8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

Preliminary T4312816A

Read & Write Cycle with Auto Precharge @ Burst Length = 4

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

H IG H

CS

RAS

CAS

ADDR

Ra

Rb Ca

Cb

BA

A 10 /A P

Ra

Rb

CL=2

DQ

CL=3

Q a0 Q a1 Q a2 Q a3

Q a0 Q a1 Q a2 Q a3

D b0 D b1 D b2 D b3

D b0 D b1 D b2 D b3

WE

DQM

R o w A ctiv e

(A -B ank)

R o w A ctiv e

(B -B ank)

R ead w ith A u to

precharge (A -

B ank)

C L = 2 A u to

P rech arg e S tart

P o in t (A -B an k )

C L = 3 A u to

P rech arg e S tart

P o in t (A -B an k )

W rite w ith A u to

P recharge (B -

B ank)

A u to P rech arg e

S tart P o in t (A -

B ank)

:D o n 't c a re

*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length = 1 & 2 and BRSW mode)

TM Technology Inc. reserves the right

P.21

to change products or specifications without notice.

Publication Date: APR. 2003

Revision: 0.B

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