T4312816A Ver la hoja de datos (PDF) - Taiwan Memory Technology

Número de pieza

componentes Descripción

fabricante

T4312816A

8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

Preliminary T4312816A

Page Write cycle at Different Bank @ Burst Length = 4

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

H IG H

CS

RAS

CAS

*N ote2

ADDR

RAa

CAa RBb

CBb

CAc

CBd

BA

A 10/A P

RAa

RBb

DQ

WE

DQM

D A a0 D A a1 D A a2 D A a3 D B b0 D B b1 D B b2 D B b3 D A c0 D A c1 D B d0 D B d1

tCDL

tRDL

*N ote1

R ow A ctive

(A -B ank)

R ow A ctive

(B -B ank)

W rite (A -

B ank)

W rite (B -

B ank)

W rite (A -

B ank)

W rite (B -

B ank)

P re c h a rg e

(A -B ank)

:D on't care

*Note : 1. To interrupt burst write by row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by row precharge, both the write and the precharge banks must be the same.

TM Technology Inc. reserves the right

P.19

to change products or specifications without notice.

Publication Date: APR. 2003

Revision: 0.B

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