STK14C88-K45M Ver la hoja de datos (PDF) - Unspecified
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componentes Descripción
fabricante
STK14C88-K45M Datasheet PDF : 12 Pages
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STK14C88-M
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
tWLQZi, j
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
tWP Write Pulse Width
tCW Chip Enable to End of Write
tDW Data Set-up to End of Write
tDH Data Hold after End of Write
tAW Address Set-up to End of Write
tAS Address Set-up to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
ADDRESS
12
tAVAV
14
tELWH
E
(VCC = 5.0V ± 10%)e
STK14C88-35M
MIN
MAX
STK14C88-45M
MIN
MAX
UNITS
35
45
ns
25
30
ns
25
30
ns
12
15
ns
0
0
ns
25
30
ns
0
0
ns
0
0
ns
13
15
ns
5
5
ns
19
tWHAX
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
20
tWLQZ
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
ADDRESS
12
tAVAV
18
tAVEL
E
14
tELEH
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
HIGH IMPEDANCE
DATA VALID
16
tEHDX
April 1999
5-46
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