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HEF4043BT,653
(Rev.:2016)

Quad R/S latch with 3-state outputs

NXP Semiconductors. 

Nexperia

HEF4043B

Quad R/S latch with 3-state outputs

6.2 Pin description

Table 2. Pin description

Symbol

1Q to 4Q

1R to 4R

1S to 4S

OE

VSS

n.c.

VDD

Pin

2, 9, 10, 1

3, 7, 11, 15

4, 6, 12, 14

5

8

13

16

7. Functional description

Description

3-state buffered latch output

reset input (active HIGH)

set input (active HIGH)

common output enable input

ground supply voltage

not connected

supply voltage

Table 3. Function table[1]

Inputs

OE

nS

nR

L

X

X

H

L

H

H

H

X

H

L

L

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance state.

8. Limiting values

Output

nQ

Z

L

H

latched

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

VDD

IIK

VI

IOK

II/O

IDD

Tstg

Tamb

Ptot

supply voltage

input clamping current

input voltage

output clamping current

input/output current

supply current

storage temperature

ambient temperature

total power dissipation

VI < 0.5 V or VI > VDD + 0.5 V

VO < 0.5 V or VO > VDD + 0.5 V

Tamb 40 C to +85 C

SO16 package

[1]

P

power dissipation

per output

[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Min

0.5

-

0.5

-

-

-

65

40

-

-

Max Unit

+18 V

10 mA

VDD + 0.5 V

10 mA

10 mA

50

mA

+150 C

+85 C

500 mW

100 mW

HEF4043B

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 11 — 24 March 2016

© Nexperia B.V. 2017. All rights reserved

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