H8S/2144 Ver la hoja de datos (PDF) - Renesas Electronics

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H8S/2144

Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

Renesas Electronics 

Main Revisions for This Edition

Item

All

1.1 Overview

Table 1.1 Overview

Page

—

4

6

Revision (See Manual for Details)

• Notification of change in company name amended

(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.

• Product naming convention amended

(Before) H8S/2148 Series → (After) H8S/2148 Group

(Before) H8S/2144 Series → (After) H8S/2144 Group

Host interface specification in table 1.1 amended

• 8-bit host interface (ISA) port

Product lineup specification in table 1.1 amended

Product Code*2

Group

Mask ROM

Versions

F-ZTAT

Versions

ROM/RAM

(Bytes)

Packages

H8S/2148

HD6432148S

HD6432148SW*1

HD64F2148

HD64F2148V*2

HD64F2148A

HD64F2148AV*2

128 k/4 k

FP-100B,

TFP-100B

HD6432147S

HD64F2147A

64 k/2 k

HD6432147SW*1 HD64F2147AV*2

H8S/2147N —

HD64F2147N

64 k/2 k

HD64F2147NV*2

H8S/2144 HD6432144S

HD64F2144

HD64F2144V*2

128 k/4 k

HD64F2144A

HD64F2144AV*2

HD6432143S

—

96 k/4 k

HD6432142

HD64F2142R

64 k/2 k

HD64F2142RV*2

Notes: 1. W indicates the I2C bus option.

2. V indicates the 3-V version. Please refer to appendix F, Product

Code Lineup.

1.2 Internal Block

7

Diagram

Figure 1.1 (a) Internal

Block Diagram of

H8S/2148 Group

Figure 1.1 (b) Internal 8

Block Diagram of

H8S/2147N

Figure 1.1 (a) amended

(Before) STBY → (After) STBY

Figure 1.1 (b) amended

(Before) IIC × 2ch → (After) IIC × 2ch (option)

Rev. 4.00 Sep 27, 2006 page vii of xliv

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