Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V724AWJ -5, -6
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read) (Note 29)
RAS
CAS
Address
W
VIH
VIL
tCRP
tRC
tRAS
tRCD
tRSH
VIH
VIL
tRAD
tASR
tRAH tASC
tCAH
VIH
ROW
COLUMN
ADDRESS
ADDRESS
VIL
tRCS
tRAL
VIH
VIL
tDZC
DQ
VIH
(INPUTS)
VIL
DQ
(OUTPUTS)
VOH
VOL
VIL
OE
VIH
tCAC
tAA
tCLZ
Hi-Z
tRAC
tDZO
tOEA
tORH
tRP
tRRH
tRC
tRAS
tRP
tCHR
tASR
ROW
ADDRESS
tCDD
Hi-Z
tOFF
DATA VALID
Hi-Z
tOEZ
tODD
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.
MIT-DS-0124-0.0
MITSUBISHI
ELECTRIC
( 15 / 20 )
26/Feb./1997