ADJD-S371-QR999 Ver la hoja de datos (PDF) - Avago Technologies

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ADJD-S371-QR999

Miniature Surface-Mount RGB Digital Color Sensor Module

Avago Technologies 

The SCL clock line synchronizes the serial data transmis-

sion on the SDA data line. It is always generated by the

master. The frequency of the SCL clock line may vary

throughout the transmission as long as it still meets the

minimum timing requirements.

The master by default drives the SDA data line. The

slave drives the SDA data line only when sending an

acknowledge bit after the master writes data to the

slave or when the master requests the slave to send

data.

The SDA data line driven by the master may be

implemented on the negative edge of the SCL clock

line. The master may sample data driven by the slave on

the positive edge of the SCL clock line. Figure shows an

example of a master implementation and how the SCL

clock line and SDA data line can be synchronized.

SDA data sampled on the

positive edge of SCL

SDA

SCL

Figure 5. Data bit synchronization

SDA data driven on the

negative edge of SCL

A complete data transfer is 8-bits long or 1-byte. Each

byte is sent most significant bit (MSB) first followed by

an acknowledge or not acknowledge bit. Each data

transfer can send an unlimited number of bytes

(depending on the data format).

SDA

MSB

S

SCL or

Sr

1

2

START or repeated

START CONDITION

Figure 6. Data byte transfer

LSB ACK MSB

8

9

1

2

P

LSB

NO

ACK

Sr

8

9

Sr

or

P

STOP or repeated

START CONDITION



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