NXP Semiconductors
74LVC244A; 74LVCH244A
Octal buffer/line driver; 3-state
5. Pinning information
5.1 Pinning
1OE 1
1A0 2
2Y0 3
1A1 4
2Y1 5
1A2 6
2Y2 7
1A3 8
2Y3 9
GND 10
74LVC244A
74LVCH244A
20 VCC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
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Fig 4. Pin configuration for SO20 and (T)SSOP20
terminal 1
index area
74LVC244A
74LVCH244A
1A0 2
2Y0 3
1A1 4
2Y1 5
1A2 6
2Y2 7
1A3 8
2Y3 9
GND (1)
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
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Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for DHVQFN20 and
DHXQFN20
5.2 Pin description
Table 2. Pin description
Symbol
Pin
Description
1OE, 2OE
1, 19
output enable input (active low)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8
data input
2Y0, 2Y1, 2Y2, 2Y3 3, 5, 7, 9
data output
GND
10
ground (0 V)
2A0, 2A1, 2A2, 2A3 17, 15, 13, 11 data input
1Y0, 1Y1, 1Y2, 1Y3, 18, 16, 14, 12 data output
VCC
20
supply voltage
74LVC_LVCH244A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 26 June 2013
© NXP B.V. 2013. All rights reserved.
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