74LV259(2016) Ver la hoja de datos (PDF) - NXP Semiconductors.

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74LV259
(Rev.:2016)

8-bit addressable latch

NXP Semiconductors. 

NXP Semiconductors

74LV259

8-bit addressable latch

9&&

05LQSXW

*1'

92+

4QRXWSXW



92/

90

W:

W3+/

90

DDK

Fig 9.

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

The conditional reset input (MR) to output (Qn) propagation delays

9&&

/(LQSXW

*1'

9&&

'LQSXW

*1'

90

WVX

WK

90

WVX

WK

92+

4QRXWSXW

4 '

90

92/

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 10. The data set-up and hold times for the D input to the LE input

4 '

DDK

9&&

$QLQSXW

*1'

9&&

/(LQSXW

*1'

90 $''5(6667$%/(

WVX

WK

90

DDK

Measurement points are given in Table 9.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig 11. The address input set-up and hold times for the An inputs to the LE input

74LV259

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 4 — 9 March 2016

© NXP Semiconductors N.V. 2016. All rights reserved.

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