AD7724(RevA) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
fabricante
AD7724 Datasheet PDF : 14 Pages
| |||
AD7724–SPECIFICATIONS1
(AVDD = 5 V ؎ 5%; DVDD = 5 V ؎ 5%, DVDD1 = 3 V ؎ 5%; AGND = DGND = 0 V,
fMCLK = 13 MHz ac-coupled sine wave, REF2A = REF2B␣ =␣ 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Integral Nonlinearity
Offset Error
Gain Error2
Offset Error Drift
Gain Error Drift
Unipolar Mode
Bipolar Mode
± 0.003
± 0.24
± 0.6
± 37.69
± 37.69
± 18.85
% FSR typ
% FSR typ
% FSR typ
µV/°C typ
µV/°C typ
µV/°C typ
When Tested with Ideal FIR Filter as in Figure 1
REF2 Is an Ideal Reference, REF1 = AGND
ANALOG INPUTS
Signal Input Span (VIN(+) – VIN(–))
Bipolar Mode
Unipolar Mode
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
REFERENCE INPUTS
REF1 Output Voltage
REF1 Output Voltage Drift
REF1 Output Impedance
Reference Buffer Offset Voltage
Using Internal Reference
REF2 Output Voltage
REF2 Output Voltage Drift
Using External Reference
REF2 Input Impedance
External Reference Voltage Range
DYNAMIC SPECIFICATIONS3
Bipolar Mode
± VREF2/2
0 to VREF2
AVDD
0
2
2 fMCLK
109/(8 fMCLK)
2.32 to 2.68
60
4
± 12
2.32 to 2.68
60
109/(16 fMCLK)
2.32 to 2.68
V max
V max
V
V
pF typ
MHz
kΩ typ
V min/max
ppm/°C typ
kΩ typ
mV max
V min/max
ppm/°C typ
kΩ typ
V min/max
Signal-to-(Noise + Distortion)
90
86
Total Harmonic Distortion
–90
Spurious Free Dynamic Range
–90
Unipolar Mode
Signal-to-(Noise + Distortion)
88
Total Harmonic Distortion
–90
Spurious Free Dynamic Range
–90
Intermodulation Distortion
–93
AC CMRR
96
dB typ
dB min
dB max
dB max
dB typ
dB typ
dB typ
dB typ
dB typ
BIP = VIH
BIP = VIL
Offset Between REF1 and REF2
REF1 = AGND
Applied to REF1 or REF2
When Tested with Ideal FIR Filter as in Figure 1
BIP = VIH, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p
or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–94.25 kHz
Input BW = 0 kHz–94.25 kHz
Input BW = 0 kHz–94.25 kHz
BIP = VIL, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V
Input BW = 0 kHz–94.25 kHz
Input BW = 0 kHz–101.556 kHz
Input BW = 0 kHz–101.556 kHz
VIN(+) = VIN(–) = 2.5 V p-p, VCM = 1.25 V to
3.75 V, 20 kHz
CLOCK
Square Wave4
MCLK Duty Ratio
VMCLKH, MCLK High Voltage
VMCLKL, MCLK Low Voltage
Sine Wave
XTAL1 Voltage Swing
45 to 55
4
0.4
0.4
4
% max
V min
V max
V p-p min
V p-p max
For Specified Operation
MCLK Uses CMOS Logic
XTAL_OFF Tied Low
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
2.4
V min
0.8
V max
10
µA max
10
pF max
–2–
REV. A
Share Link: 