2645L8 Ver la hoja de datos (PDF) - Linear Technology
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2645L8 Datasheet PDF : 20 Pages
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LTC2645
Operation
If IDLSEL is connected to VCC, any channel or all chan-
nels can be powered down by keeping the PWM input(s)
(INA/INB/INC/IND) low for the idle mode timeout delay t3.
The integrated reference is automatically powered down
when external reference mode is selected or when all DAC
channels are powered down. In addition, all the DAC chan-
nels and the integrated reference can be powered down
by pulling the PD pin low. When the integrated reference
is powered down, the REF pin becomes high impedance
(typically > 1GΩ).
Normal operating current resumes when PD returns high
for transparent operation (IDLSEL = GND). For sample/
hold operation (IDLSEL = VCC), the LTC2645 remains
in full power-down until the first rising edge is received
on any PWM input. Any pair of PWM input rising edges
separated by less than the idle mode timeout delay t3
(50ms minimum) will cause the DAC code to be updated.
The DAC output(s) will remain in Hi-Z until the channel
is updated following the second rising PWM input edge.
Voltage Output
The LTC2645’s integrated rail-to-rail amplifier has guar-
anteed load regulation when sourcing or sinking up to
10mA at 5V, and 5mA at 3V.
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load current. The measured change in output voltage per
change in forced load current is expressed in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ω. The amplifier’s DC output imped-
ance is 0.1Ω when driving a load well away from the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 50Ω typical channel resistance of the output devices
(e.g., when sinking 1mA, the minimum output voltage is
50Ω • 1mA, or 50mV). See the graph Headroom at Rails
vs Output Current in the Typical Performance Character-
istics section.
The amplifier is stable driving capacitive loads of up to
500pF.
Rail-to-Rail Output Considerations
In any rail-to-rail voltage output device, the output is limited
to voltages within the supply range.
Since the analog output of the DAC cannot go below
ground, it may limit the lowest codes reachable as shown
in Figure 2b. Similarly, limiting can occur near full-scale
when the REF pin is tied to VCC. If VREF = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC, as shown in Figure 2c. No full-scale
limiting will occur if VREF is less than VCC–FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Board Layout
The PC board should have separate areas for the analog and
digital sections of the circuit. A single, solid ground plane
should be used, with analog and digital signals carefully
routed over separate areas of the plane. This keeps digital
signals away from sensitive analog signals and minimizes
the interaction between digital ground currents and the
analog section of the ground plane. The resistance from
the LTC2645 GND pin to the ground plane should be as
low as possible. Resistance here will add directly to the
effective DC output impedance of the device (typically
0.1Ω). Note that the LTC2645 is no more susceptible to
this effect than any other parts of this type; on the con-
trary, it allows layout-based performance improvements
to shine rather than limiting attainable performance with
excessive internal resistance.
2645f
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For more information www.linear.com/LTC2645
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