TDA10045H Ver la hoja de datos (PDF) - Philips Electronics
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TDA10045H Datasheet PDF : 20 Pages
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Philips Semiconductors
DVB-T channel receiver
Product specification
TDA10045H
SYMBOL
PIN
FFT_WIN
30
VDDD33
31
VSSD
32
SACLK
33
FI[9:5]
34 to 38
VDDD18
VSSD
FI[4:0]
39
40
41 to 45
VDDD50
46
VSSD
47
IT
48
FEL
49
n.c.
50
n.c.
51
TRSTN
52
TMS
53
TDI
54
TCK
55
TDO
56
VDDD18
57
VSSD
58
DS_SPARE2
59
DS_SPARE1
60
VDDD33
61
VSSD
62
UNCOR
63
PSYNC
64
TYPE
I/O
−
−
O
I/O
−
−
IO
−
−
OD(1)
OD(1)
−
−
I(2)
I(2)
I(2)
I(2)
O
−
−
O
O
−
−
O
O
DESCRIPTION
output or input signal indicating the start of the active data; equals 1 during
complex sample 0 of the active FFT block; can be used to synchronize 2 chips
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V)
sampling frequency output; this output clock can be fed to an external (10-bit)
ADC as a sampling clock; SACLK can also provide twice the sampling clock
input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
−512 to +511). In internal ADC mode, these outputs can be used to monitor
extra demodulator output signals (constellation or frequency response).
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
input data from an external ADC, FI must be tied to ground when unused,
positive notation (from 0 to 1023) or twos complement notation (from
−512 to +511). In internal ADC mode, these outputs can be used to monitor
extra demodulator output signals (constellation or frequency response).
digital supply voltage (5 V typ.); can be set to 3.3 V (with caution) if 5 V tolerant
I/O is not required
digital ground supply (0 V)
interrupt line; this output interrupt line can be configured by the I2C-bus
interface. This pin is an open-drain output and therefore requires an external
pull-up resistor (to VDDD33 or VDDD50).
front-end lock; FEL is an open-drain output and therefore requires an external
pull-up resistor (to VDDD33 or VDDD50)
not connected
not connected
asynchronous reset signal for boundary scan; connected to GND if not used
mode programming signal for boundary scan; connected to GND if not used
input port for boundary scan; connected to GND if not used
clock signal for boundary scan; connected to GND if not used)
output port for boundary scan; not connected if not used
digital supply voltage for the core (1.8 V typ.)
digital ground supply (0 V)
spare delta-sigma output; managed by the DSP or by an I2C-bus register to
generate an analog level (after a RC low-pass filter)
spare delta-sigma output; managed by the DSP to handle a low frequency DAC
(automatic first stage tuner AGC measurement or 2nd AGC loop control as
examples)
digital supply voltage for the pads (3.3 V typ.)
digital ground supply (0 V)
RS error flag, active HIGH on one RS packet if the RS decoder fails to correct
the errors
pulse synchro; this output signal goes HIGH on a rising edge of OCLK when a
synchro byte is provided, then goes LOW until the next synchro byte
2001 Nov 08
6
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