X40035SC Ver la hoja de datos (PDF) - Intersil

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X40035SC

Triple Voltage Monitor with Integrated CPU Supervisor

Intersil 

X40030, X40031, X40034, X40035

Timing Diagrams

Bus Timing

tF

tHIGH

tLOW

tR

SCL

tSU:STA

SDA IN

tHD:STA

tSU:DAT

SDA OUT

tHD:DAT

tAA tDH

WP Pin Timing

SCL

SDA IN

WP

START

tSU:WP

CLK 1

SLAVE ADDRESS BYTE

CLK 9

tHD:WP

Write Cycle Timing

SCL

tSU:STO

tBUF

SDA

8TH BIT OF LAST BYTE

ACK

tWC

STOP

CONDITION

START

CONDITION

Nonvolatile Write Cycle Timing

SYMBOL

tWC

(Note 11)

PARAMETER

Write Cycle Time

MIN

MAX

(Note 3)

TYP

(Note 3)

UNIT

5

10

ms

NOTE:

11. tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is the

minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

18

FN8114.2

August 25, 2008

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