X40020SZIA Ver la hoja de datos (PDF) - Intersil

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X40020SZIA

Dual Voltage Monitor with Integrated CPU Supervisor and System Battery Switch

Intersil 

X40020, 40021

Figure 13. Slave Address, Word Address, and Data Bytes

Slave Byte

General Purpose Memory 1 0 1 0 0 0 A8 R/W

Control Register

1 0 1 1 0 0 1 R/W

Fault Detection Register 1 0 1 1 0 0 0 R/W

Word Address

General Purpose Memory A7 A6 A5 A4 A3 A2 A1 A0

Control Register

111 11111

Fault Detection Register 1 1 1 1 1 1 1 1

Word Address

The word address is either supplied by the master or

obtained from an internal counter.

Operational Notes

The device powers-up in the following state:

– The device is in the low power standby state.

– The WEL bit is set to ‘0’. In this state it is not possi-

ble to write to the device.

– SDA pin is the input mode.

– RESET/RESET Signal is active for tPURST.

Data Protection

The following circuitry has been included to prevent

inadvertent writes:

– The WEL bit must be set to allow write operations.

– The proper clock count and bit sequence is required

prior to the stop bit in order to start a nonvolatile

write cycle.

– A three step sequence is required before writing into

the Control Register to change Watchdog Timer or

Block Lock settings.

– The WP pin, when held HIGH, prevents all writes to

the array and all the Register.

14

FN8112.1

May 17, 2006

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