WM8785(2005) Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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fabricante

WM8785
(Rev.:2005)

24-Bit, 192kHz Stereo ADC

Wolfson Microelectronics plc 

WM8785

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Pre-Production

Figure 1 System Clock Timing Requirements

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

System Clock Timing Information

MCLK System clock cycle time

MCLK duty cycle

SYMBOL

TMCLKY

TMCLKDS

MIN

25

60:40

TYP

MAX

UNIT

ns

40:60

AUDIO INTERFACE TIMING – MASTER MODE, PCM DATA

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.

PARAMETER

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

DOUT propagation delay from BCLK falling edge

SYMBOL

tDL

tDDA

MIN

TYP

MAX

UNIT

0

10

ns

0

11

ns

w

PP Rev 3.0 December 2005

8

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