W9816G6BB-7 Ver la hoja de datos (PDF) - Winbond
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W9816G6BB-7 Datasheet PDF : 43 Pages
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W9816G6BB
5. BALL DESCRIPTION
BALL-LOCATION
BALL
NAME
FUNCTION
DESCRIPTION
N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7
A0 − A10
Address
Multiplexed pins for row and column address.
Row address: A0 − A10. Column address: A0 − A7.
M1
BA
Bank
Address
Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.
A6, B7, C7, D7, D6,
E7, F7, G7, G1, F1,
E1, D2, D1, C1, B1,
A2,
DQ0 −
DQ15
Data Input/
Output
Multiplexed pins for data input and output.
Disable or enable the command decoder. When
L7
CS
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
K6
Row Address
RAS
Strobe the clock, RAS , CAS and WE define the
operation to be executed.
Column
K7
CAS
Address Referred to RAS
Strobe
J7
WE Write Enable Referred to RAS
J2/J6
UDQM/
LDQM
The output buffer is placed at Hi-Z (with latency of 2)
Input/Output when DQM is sampled high in read cycle. In write
Mask cycle, sampling DQM high will block the write
operation with zero latency.
K2
CLK
Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
L1
CKE Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
A7, R7
VDD
Power Power for input buffers and logic circuit inside
(+3.3V) DRAM.
A1, R1
VSS
Ground
Ground for input buffers and logic circuit inside
DRAM.
B6, C2, E6, F2
VDDQ
Power
(+3.3V) for
I/O buffer
Separated power from VDD, used for output buffers
to improve noise immunity.
B2, C6, E2, F6
VSSQ
Ground for Separated ground from VSS, used for output buffers
I/O buffer to improve noise immunity.
G2, G6, H1, H2, H6,
H7, J1, K1, L2, L6,
NC
M6, M7
No
Connection
No connection
Publication Release Date: January 2, 2003
-5-
Revision A1
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