VG36648041DTL-7L Ver la hoja de datos (PDF) - Unspecified

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VG36648041DTL-7L

CMOS Synchronous Dynamic RAM

Unspecified 

VIS

VG36644041DT / VG36648041DT / VG36641641DT

CMOS Synchronous Dynamic RAM

DC Characteristics 1

(Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V, VSS = VSSQ = 0V, Ouput Open, unless otherwise noted)

Parameter

Symbol

Test Conditions

Organization

-6

Limits (max.)

-7

-7L

Operating current

ICC1

One bank active

tRC = tRC(MIN), tCLK = tCLK(MIN),

BL = 1, CL=3

x4

-

75

75

x8

-

75

75

x16

95

85

85

Precharge standby ICC2P CKE ≤ VIL(MAX), tCK = 15ns

x4/x8/x16

2

current in power down

mode

ICC2PS

CKE ≤ VIL(MAX), CLK ≤ VIL(MAX)

x4/x8/x16

1

Precharge standby

current in non power

down mode

ICC2N

CCKSE ≥ VCC - 0.2V

tCK = 15ns, CCKKEE ≥ VIH(MIN)

x4/x8/x16

20

ICC2NS CCKSE ≥ VCC - 0.2V

CLK ≤ VIL(MAX),CCKKEE ≥ VVIH(MIN)

x4/x8/x16

15

All input signals are stable.

Active standby current ICC3P CKE ≤ VIL(MAX), tCK = 10ns

x4/x8/x16

7

in power down mode ICC3PS CKE ≤ VIL(MAX), CLK ≤ VIL(MAX)

x4/x8/x16

5

Active standby current ICC3N

in Nonpower down

mode

CCKSE ≥ VCC - 0.2V

tCK = 15ns, CCKKEE ≥ VIH(MIN)

x4/x8/x16

30

ICC3NS CCKSE ≥ VCC - 0.2V

CLK ≤ VIL(MAX),CCKKEE ≥ VVIH(MIN)

x4/x8/x16

25

All input signals are stable.

Operating current

ICC4

All banks active

(Burst mode)

tCK = tCK(MIN), BL=4, CL=3

All banks active

x4

-

90

90

x8

-

90

90

x16

130 100 100

Refresh current

ICC5

tRC = tRC(MIN), tCLK = tCLK(MIN)

x4/x8/x16 150 130 130

Self refresh current ICC6

CKE ≤ 0.2V

1

x4/x8/x16

0.5

NOTES

1. ICC(max) is specified at the output open condition.

2. -6 grade is available only on 4MX16 option.

3. Input signals are changed one time during 30ns.

4. Normal version: VG366440(80/16)41DT

5. Low power version: VG366440(80/16)41DTL

Unit Notes

-8H

70

70 mA 1, 2

80

mA

mA 3

mA

mA

mA 3

mA

70

70 mA

80

110 mA

mA 4

mA 5

DC Characteristics 2

(Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)

Parameter

Symbol

Test Condition

Input leakage current (Inputs)

II (L) 0 ≤ VIN ≤ VDD(MAX)

Pins not under test = 0V

Output leakage current (I/O pins)

IO (L)

0 ≤ VOUT ≤ VDD(MAX)

DQ# in H - Z., DOUT is disabled

High level output voltage

VOH IOH = -2mA

Low level output voltage

VOL IOL = 2mA

Min

Max

Unit

-5

5

uA

-5

5

uA

2.4

V

0.4

V

Document :1G5-0177

Rev.2

Page 6

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