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V53C8126H40

ULTRA-HIGH PERFORMANCE, 128K X 8 BIT FAST PAGE MODE CMOS DYNAMIC RAM

Mosel Vitelic Corporation  

MOSEL VITELIC

Fast Page Mode Operation

Fast Page Mode operation permits all 256

columns within a selected row of the device to be

randomly accessed at a high data rate. Maintaining

RAS low while performing successive CAS cycles

retains the row address internally and eliminates

the need to reapply it for each cycle. The column

address buffer acts as a transparent or flow-through

latch while CAS is high. Thus, access begins from

the occurrence of a valid column address rather

than from the falling edge of CAS, eliminating tASC

and tT from the critical timing path. CAS latches the

address into the column address buffer and acts as

an output enable. During Fast Page Mode

operation, Read, Write, Read-Modify-Write or

Read-Write-Read cycles are possible at random

addresses within a row. Following the initial entry

cycle into Fast Page Mode, access is tCAA or tCAP

controlled. If the column address is valid prior to the

rising edge of CAS, the access time is referenced to

the CAS rising edge and is specified by tCAP. If the

column address is valid after the rising CAS edge,

access is timed from the occurrence of a valid

address and is specified by tCAA. In both cases, the

falling edge of CAS latches the address and

enables the output.

Fast Page Mode provides sustained data rates

up to 40 MHz for applications that require high data

rates such as bit-mapped graphics or high-speed

signal processing. The following equation can be

used to calculate the maximum data rate:

Data Rate =

256

tRC + 255 x tPC

Data Output Operation

The V53C8126H Input/Output is controlled by

OE, CAS, WE and RAS. A RAS low transition

enables the transfer of data to and from the

selected row address in the Memory Array. A RAS

high transition disables data transfer and latches

the output data if the output is enabled. After a

memory cycle is initiated with a RAS low transition,

a CAS low transition or CAS low level enables the

internal I/O path. A CAS high transition or a CAS

high level disables the I/O path and the output driver

if it is enabled. A CAS low transition while RAS is

high has no effect on the I/O data path or on the

output drivers. The output drivers, when otherwise

enabled, can be disabled by holding OE high. The

V53C8126H

OE signal has no effect on any data stored in the

output latches. A WE low level can also disable the

output drivers when CAS is low. During a Write

cycle, if WE goes low at a time in relationship to

CAS that would normally cause the outputs to be

active, it is necessary to use OE to disable the

output drivers prior to the WE low transition to allow

Data In Setup Time (tDS) to be satisfied.

Power-On

After application of the VCC supply, an initial

pause of 200 µs is required followed by a minimum

of 8 initialization cycles (any combination of cycles

containing a RAS clock). Eight initialization cycles

are required after extended periods of bias without

clocks (greater than the Refresh Interval).

During Power-On, the VCC current requirement of

the V53C8126H is dependent on the input levels of

RAS and CAS. If RAS is low during Power-On, the

device will go into an active cycle and IDD will exhibit

current transients. It is recommended that RAS and

CAS track with VCC or be held at a valid VIH during

Power-On to avoid current surges.

Table 1. V53C8126H Data Output

Operation for Various Cycle Types

Cycle Type

I/O State

Read Cycles

CAS-Controlled Write

Cycle (Early Write)

WE-Controlled Write

Cycle (Late Write)

Read-Modify-Write

Cycles

Fast Page Mode

Read

Fast Page Mode Write

Cycle (Early Write)

Fast Page Mode Read-

Modify-Write Cycle

RAS-only Refresh

CAS-before-RAS

Refresh Cycle

CAS-only Cycles

Data from Addressed

Memory Cell

High-Z

OE Controlled. High

OE = High-Z I/Os

Data from Addressed

Memory Cell

Data from Addressed

Memory Cell

High-Z

Data from Addressed

Memory Cell

High-Z

Data remains as in

previous cycle

High-Z

V53C8126H Rev. 1.1 July 1997

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