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UPD98409GN-LMU

ATM LIGHT SAR CONTROLLER

NEC => Renesas Technology 

µPD98409

1. PIN FUNCTION

The pin function of the µPD98409 is descibed below. A detailed explanation of how to use each pin, and the

points to be noted in using the pins are given in µPD98409 User’s Manual (Document Number: S12776E). Be sure

to refer to this user’s manual.

The following describes the I/O levels in the tables.

LV-TTL input : Can be connected to 5 V CMOS output

TTL output : Can be connected to 5 V TTL input, VOH = 3.3 V, IOL = 6 mA

CMOS output : 3.3 V CMOS output, VOH = 3.3 V, IOL = 12 mA

PCI input : 5/3.3 V PCI input

PCI output : 5/3.3 V PCI output

1.1 PHY Device Interface Pin

PHY device interfaces include a UTOPIA interface through which the µPD98409 transfers ATM cells with a PHY

device, and a PHY control interface by which the µPD98409 controls the PHY device.

1.1.1 UTOPIA interface

Pin Name

Pin No.

I/O

Rx7-Rx0

116 - 119,

I

123 - 126

RSOC

133

I

RENBL_B

132

O

EMPTY_B/

131

I

RxCLAV

RCLK

128

O

Tx7-Tx0

141 - 144,

O

146 - 149

TSOC

135

O

I/O Level

LV-TTL

LV-TTL

TTL

LV-TTL

TTL

TTL

TTL

(1/2)

Function

Receive Data Bus.

Rx7 through Rx0 constitute an 8-bit input bus which inputs data

received from a network in byte format from a PHY device. The

µPD98409 loads data in at the rising edge of RCLK.

Receive Start Cell.

The RSOC signal is input in synchronization with the first byte of the

cell data from a PHY device. This signal remains high while the first

byte of the header is input to Rx7 through Rx0.

Receive Enable.

The RENBL_B signal indicates to a PHY device that the µPD98409 is

ready to receive data in the next clock cycle.

PHY Output Buffer Empty/Rx Cell Available.

This signal notifies the µPD98409 that there is no cell data to be

transferred in the receive FIFO and that no receive data can be

supplied to the PHY device. When the UTOPIA interface is in the

octet-level handshake mode, this signal serves as EMPTY_B,

indicating that the data on Rx7 through Rx0 are invalid in the current

clock cycle. In the cell-level handshake mode, it serves as RxCLAV,

indicating that there is no cell to be supplied next after the transfer of

the current cell is completed.

Receive Clock.

This is a synchronization clock used to transfer cell data with the PHY

device at the receive side. The system clock input to the BUSCLK pin

is output from this pin as is.

Transmit Data Bus.

Tx7 through Tx0 constitute an 8-bit output bus which outputs transmit

data in byte format to a PHY device. The µPD98409 outputs data at

the rising edge of TCLK.

Transmit Start of Cell.

The TSOC signal is output in synchronization with the first byte of

transmit cell data.

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