CXD2027R Ver la hoja de datos (PDF) - Sony Semiconductor

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componentes Descripción

fabricante

CXD2027R

DBS Audio Signal Processor

Sony Semiconductor 

Bit stream signal interface

CK2M

BITO

BITO is output at falling sync.

2048 1

2

3

4

2047 2048 1

2

Data interface after BCH error correction

CK2M

FRAM

DATO

DATO is output at falling sync.

2048 1 2 3 4

2047 2048 1 2

1ms

1 frame

CXD2027Q/R

Examples of error detection countermeasures for low C/N control sign and chargeable flag integration

detection

When C/N is low, NSYN frequently goes high level (asynchronous state).

In this case, problems such as wrong display or wrong detection of control sign 7th bit "broadcast/non-

broadcast" flag may occur due to incorrect integration detection. This can be improved using the

microcomputer software shown below.

Integration detection result can be updated only when NSYN is low level. Detection results of this IC are read

by the standard trigger of the microcomputer, and if the result values match for 5 to 6 times continuously, the

detection result is taken as an update for the system. It is also possible to update the integration detection

result by the continuous matching of 7 times or more. However, standard trigger cycle of the microcomputer

must be set about 18ms.

NSYN

Control sign,Chargeable flag

(IC)

Control sign,Chargeable flag

(microcomputer)

→ integration detection results

Standard trigger

(microcomputer)

18ms

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